1. Field of the Invention
This invention relates to a test pattern generating apparatus which generates an address pattern and a data pattern for testing semiconductor memory systems.
2. Description of the Prior Art
To test a semiconductor memory, data is written in the semiconductor memory under test at a storage location specified by addressing and subsequently data at each storage location of the memory is read for comparison with an expected value to check whether or not the data read out is identical to the expected value, thereby checking whether the semiconductor memory functions properly or not. Such a test is accomplished by performing complicated operations, for example, repeatedly reading out the memory with data stored only at one address but no data at all the other addresses while shifting the single data storage location one by one for each memory readout. To perform this, it is customary to successively generate addresses as patterns together with various data corresponding thereto.
For such address pattern generation and data generation, a memory containing a microprogram is read to interpret and execute the program, thereby to generate an address pattern generate instruction, a data pattern generate instruction, a memory control instruction, etc. In accordance with these instructions, an address pattern generation section generates an address pattern by performing calculation pursuant to the address pattern generate instruction and a data pattern generation section generates a data pattern by performing an operation pursuant to the data pattern generate instruction. There has also been proposed a test system in which combinations of such address and data patterns are all prestored in a memory and read out therefrom for input into a memory under test. With such a storage memory system, the capacity of the memory for storing the test patterns inevitably becomes markedly large, especially in the case of testing a large capacity semiconductor memory. To avoid this, the abovesaid method of pattern generation by calculation is usually employed for testing a large capacity semiconductor memory. Such a semiconductor memory test apparatus is disclosed in U.S. Pat. No. 3,751,649 patented Aug. 7, 1973, entitled "Memory System Exerciser".
In the test pattern generator heretofore employed, the address pattern generation and the data pattern generation are performed entirely independently of each other and pattern generation sections are completely placed under program control; this imposes limitations on the pattern generation. It is effective to conduct a galloping, walking or like pattern memory test such that a special data pattern is generated in a memory area of the semiconductor memory under test, but there is a limit to complicated generation of a such a complicatedly changing address. The data pattern generation also has its limit. For example, it is effective, in itself, to test the semiconductor memory by inverting data and addressing a certain memory area of the semiconductor memory under test, but this needs a huge program for generating data patterns. Therefore, no heed has heretofore been taken of such a test which employs galloping, walking or like addressing and which inverts data stored at a specified memory area.
For a semiconductor memory in which each word is composed of a plurality of bits, it is effective to test the semiconductor memory by inverting or holding unchanged all data patterns to be written in the memory and, in the prior art, the inversion and non-inversion of the data patterns are accomplished under program control. But it is difficult to write data in the memory under test, inverting or holding them unchanged, and to test the influence of writing on addresses adjoining the accessed ones. In the prior art, since the inversion of the data to be written in the memory under test is conducted under program control, it is very important to invert only a specified one or more bits of one word of the data, thereby to test interference in the word and the influence on the adjoining words. In the past, however, such a test has not been conducted. The reason is that this test also has not been taken into account because a markedly complicated program is needed for the inversion control of a desired one or more bits of one word since all operations are achieved under program control.
For testing semiconductor memories, the galloping or walking test is effective, as described previously, and is convenient because it is regular and because the address pattern can be generated by calculation. In this test, however, even if a fault is found in the memory under test, it is difficult to precisely locate the fault. To solve this problem, there has heretofore been employed, as fault separation test patterns, special patterns with which it is possible to isolate the respective functions of a sense-amplifier, an address decoder, a memory cell, etc. formed in the memory. This test pattern cannot be generated by calculation because it lacks regularity in address generation. Accordingly, it is customary to prestore such special test patterns in a memory in the order of generation and to successively read them for input to a memory under test. To perform this, a test pattern generator for reading the patterns stored in the memory is prepared separately from the device for generating test patterns by calculation. In the case of testing a memory by supplying thereto the test patterns, switching over the two test pattern generators to each other, the so-called dummy cycle occurs at the time of switching, making it impossible to continuously test the memory in its cycle time. If such a dummy cycle exists, there is a fear that the internal state of the memory under test may be altered in the dummy cycle; so no accurate test can be accomplished. That is, an accurate memory test cannot be effected unless it is continuously performed at the operating speed of the memory under test. In the prior art, however, it is imposssible to accomplish such a memory test by continuously generating test patterns while switching over the operation type test pattern generator and the storage type test pattern generator between each other.
In this kind of test pattern generating apparatus, as the operating speed of the memory under test increases, it becomes more difficult to decide whether the test pattern being generated is proper or not. However, no accurate test can be accomplished unless an accurate test pattern is generated; therefore, it is important to decide if the test pattern is being generated properly. In the past, it has not been checked during test whether the patterns being generated are correct or not. Accordingly, it might be said that such a test pattern generating apparatus is low in reliability. It is important to check whether the test patterns are being generated correctly or not, and to this end, the so-called pattern trace test has heretofore been employed. This is to successively trace test patterns one by one so as to check whether the patterns being generated are correct or not; namely, the test patterns are generated in sequence to allow for checking. Accordingly, in this pattern trace test, the test patterns are not generated at the operating speed of the memory under test.
But it is also important to generate and check test patterns one by one. Such checking of all the test patterns is important but, in the prior art, pattern tracing is accomplished only in a portion of a test pattern suspected to include an error, thereby to check the pattern. To perform this, in the prior art, a test pattern generation program is executed by simulation until the pattern trace starting position is reached and then pattern trace is initiated. However, since the program proceeds by simulation, that is, by logic, a relatively long time is required until the pattern trace starting position is reached and consequently generated test patterns cannot be checked efficiently.
This kind of test pattern generating apparatus is designed so that prior to or during test, a variety of data are set, for instance, from an electronic computer for calculation based on the set data. Unless the data thus set in the test pattern generating apparatus is correct, correct test patterns cannot be generated. A method that has been employed in the past for checking the data is to write the data in a register in a transfer cycle and to read the data in the next cycle for checking whether they are correct or not. Accordingly, two device cycles are required for transferring one set of data, so that in the data transfer cycle during which the test pattern generating apparatus is in operation it is impossible to check whether the data is transferred correctly or not. Further, for checking the transferred data, a read cycle is required, for which transfer operation takes much time.
The memory under test is sometimes accessed, for example, with a row address being fixed but a column address being successively changed, and in addition, in some types of memories, the row and column addresses are received by common terminals, and the addresses being supplied alternately with each other are distributed as row and column addresses. A system for testing such memories, with the row address being fixed and the column address being changed, is referred to as a page mode test. For automatic execution of such a page mode test, it is necessary for a programmer to make a page mode test program, bearing in mind that the row address is retained unchanged, which imposes a great burden on him. Especially in the case of changing at least one of the addresses at random, it is almost impossible to make a program so one of the addresses is fixed and that the other is varied. Therefore, the page mode test cannot be made in such a case where one of the addresses is fixed.
The generation of the row and column addresses by calculation, has been achieved under program control in the past to successively generate, for example, row addresses and to detect them when they have reached a boundary value and then to generate a column address by calculation. In this case, the program becomes longer in that the storage capacity for storing the program increases and the program requires much time for pattern generation.